In semiconductor devices, strained germanium (s-Ge), strained silicon (s-Si), and strained silicon germanium (s-SiGe) layers are very promising as future transistor channel materials. Devices such as metal oxide semiconductor field effect transistors (MOSFETs) have been experimentally demonstrated to exhibit enhanced device performance compared to devices fabricated using conventional (unstrained) silicon substrates. Potential performance improvements include increased device drive current and transconductance, as well as the added ability to scale the operation voltage, without sacrificing circuit speed, in order to reduce power consumption.
In general, formation of strained layers is the result of strain induced in these layers when they are grown on a substrate formed of a crystalline material whose lattice constant is greater or smaller than that of the strained layers. The lattice constant of Ge is about 4.2 percent greater than that of Si, and the lattice constant of a SiGe alloy is linear with respect to its Ge concentration. In one example, the lattice constant of a SiGe alloy containing fifty atomic percent Ge is about 1.02 times greater than the lattice constant of Si.
Overlying the channel material in a MOSFET is a gate dielectric material, and a gate electrode material overlies the gate dielectric material. The gate dielectric material can include a Si-containing dielectric layer such as a SiO2, SiON, or SiN dielectric layers, either used alone as a gate dielectric layer or as an interfacial layer in combination with a high-k dielectric material that offers improved gate leakage properties. Many high-k dielectric materials have poor interface properties compared to Si-containing dielectric layers, particularly oxidized Si layers and therefore an ultra thin oxidized Si-containing interfacial layer is typically inserted below the high-k dielectric material above the channel material.
Current methods for forming Si-containing dielectric layers such as ultra thin oxidized Si layers typically require high temperature oxidation processes in order to achieve the desired electrical properties of the ultra thin oxidized Si layers. Currently, substrate temperatures above 700° C. are required, for example substrate temperatures of 800° C. or higher. Such high substrate temperatures have been observed to result in defect formation due to at least partial strain relaxation in strained Ge-containing channel materials such as Ge and SiGe, and/or partial oxidation of the strained Ge-containing layer. Furthermore, since the ultra thin oxidized Si layers can be only a few monolayers thick, the strained Ge-containing layers underneath the oxidized Si layer may be damaged by highly energetic plasma species during conventional plasma oxidation.